Interface circuits for interfacing an output stage of a digital signal processing device with a data bus, and in particular with a shared data bus, for outputting digital data onto the data bus are known. Such interface circuits must comply with the operating transmission standard of the data bus. Such transmission standards are, for example, RS485, RS422, RS232 and CANbus standards. Such standards permit the voltage on the data bus and in particular the common mode voltage of different signals to vary within relatively wide voltage ranges. For example, the RS485 standard permits the common voltage of differential signals to vary between +12 volts and −7 volts. Indeed, some transmission standards permit differential data buses to operate with common mode voltages within voltage ranges wider than the permitted voltage range of the RS485 standard. Many digital signal processing devices operate at relatively low supply voltages, for example, laptop computers operate with a supply voltage of 5 volts, and may operate with supply voltages as low as 3 volts. Indeed, the majority of CMOS and BiCMOS circuits operate at supply voltages between 3 volts and 5 volts. Accordingly, interface circuits for interfacing an output stage of a digital signal processing device to a data bus operating within the RS485 transmission standard or other transmission standards which permit common mode voltages within a relatively wide voltage range must be capable of presenting a high impedance to the data bus over at least the permitted voltage range of the data bus, in order to avoid currents being sourced to the data bus from the interface circuit or vice versa.
Additionally, the RS485 transmission standard and other transmission standards require that a data output signal produced by an interface circuit for applying to the data bus be produced with a relatively high voltage swing between the logic high level and the logic low level. For example, the RS485 standard requires that the data output signal deliver a differential output voltage of 1.5 volts across a differential load resistor of 54 ohms. Accordingly, low voltage circuits, for example, CMOS and BiCMOS output stage interface circuits operating with a 3 volt supply require that the on-resistance of driver transistors which drive the data output terminal of such interface circuits to the logic high and logic low voltage levels be relatively low, in order to provide the necessary output voltage swing. This requires that the die area of the driver transistors be sufficient to produce the appropriate relatively low on-resistance.
A typical elementary prior art output stage interface circuit, which is implemented by a CMOS process is illustrated in FIG. 1, and is indicated generally by the reference numeral 100. Power supply rails, namely, a first rail 101, and a second rail 102 receive a power supply, typically a 3 volt power supply VDD. The first rail 101 is held at ground, and the positive supply voltage VDD is applied to the second rail 102. Digital data is outputted onto a data bus (not shown) through a data output terminal 103. An NMOS transistor 105 couples the data output terminal 103 to the first rail 101, and a PMOS transistor 106 couples the data output terminal 103 to the second rail 102. A data control circuit 107 in response to digital data inputted from a digital signal processing circuit (not shown) outputs first and second data control signals to gates of the respective NMOS and PMOS transistors 105 and 106, respectively, for selectively operating the transistors 105 and 106 for determining the logic high and logic low voltage states of the data output terminal 103, for in turn outputting the data in digital form onto the data bus, and also for simultaneously disabling the NMOS and PMOS transistors 105 and 106, in other words, for simultaneously holding the transistors 105 and 106 in the off-state during periods when data is not being outputted to the data bus.
In this specification the terms “on-state” and “off-state” when used in conjunction with a transistor are used to refer to the low impedance state and the high impedance state, respectively, of the transistor. Additionally, the term “diode voltage drop” when used in this specification is used to refer to the threshold voltage at which a diode commences to conduct current, and as will be understood by those skilled in the art, is dependent on the types of P-type and N-type materials from which the diode junction is formed, and in general, ranges from 0.3 volts to 0.7 volts.
However, a problem with the prior art interface circuit 100 occurs when the voltage on the data output terminal 103 is pulled by the voltage on the data bus to a voltage above the supply voltage VDD on the second rail 102, or below the ground voltage on the first rail 101. Once the voltage on the data output terminal 103 is pulled by the voltage on the data bus above the supply voltage VDD on the second rail 102 by a diode voltage drop of approximately 0.7 volts, a parasitic diode Dp1 between the back gate and the drain of the PMOS transistor 106 becomes sufficiently forward biased to conduct, and since the back gate of the PMOS transistor 106 is shorted to the source, current is sourced from the data bus to the interface circuit. Additionally, when the voltage on the data output terminal 103 is pulled by the voltage on the data bus to a voltage below the ground voltage on the first rail 101 by a diode voltage drop of approximately −0.7 volts, a parasitic diode Dp2 between the back gate and the drain of the NMOS transistor 105 becomes sufficiently forward biased to conduct, and since the back gate of the NMOS transistor 105 is shorted to the source, current is sourced from the interface circuit to the data bus. Neither of these conditions is permissible.
Output stage interface circuits which have overcome the problem of sourcing current to and from the data bus are disclosed in U.S. Pat. No. 5,966,041 of Brian Moane, and in U.S. Pat. No. 5,414,314 of Charles Thurber. However, in the interface circuit disclosed in U.S. Pat. No. 5,966,041 of Moane, two NMOS transistors coupled in series between the data output terminal and the ground rail determine the logic low voltage state of the data output terminal. The two NMOS transistors are arranged in series in order to prevent current being sourced from the interface circuit to the data bus, when the voltage on the data bus drops below the ground voltage on the ground rail. The disadvantage of providing two MOS transistors in series is that the on-resistance of the two MOS transistors must each be half the on-resistance of a single MOS transistor in order that the data output terminal can be driven with the same output voltage swing as with a single MOS transistor. However, in order to halve the on-resistance of a MOS transistor, the size of the MOS transistor must be doubled. Thus, the die area required by the two NMOS transistors of the interface circuit of Moane is four times that which would be required by the NMOS transistor 105 of the prior art interface circuit 100 of FIG. 1.
The interface circuit disclosed in U.S. Pat. No. 5,414,314 of Thurber also requires two NMOS transistors to be coupled in series between the data output terminal and the ground rail, and also requires two PMOS transistors to be coupled between the data output terminal and the high voltage rail of the supply voltage. Accordingly, the die area required by the interface circuit of Thurber is four times that which would be required for the prior art interface circuit 100 of FIG. 1.
With the premium being currently placed on die area in most integrated circuits, and in particular, in CMOS circuits, the quadrupling of the die area required by the two MOS transistors which couple the data output terminal to the ground rail of the interface circuit of Moane, and the quadrupling of the die area required by the interface circuit of Thurber is undesirable. There is therefore a need for an output stage interface circuit which addresses this problem.
The present invention is directed towards providing such an output stage interface circuit, and the invention is also directed towards a method for operating an output stage interface circuit which addresses the problem of prior art output stage interface circuits.